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verilogsystem-verilogmodelsim

$sscanf : Invalid format specifier '

I'm trying to port a rather big testbench from VCS to QuestaSim, and while everything works in VCS, there are some problems when porting it. The latest error I get when running vsim is $sscanf: Invalid format specifier '.

It fails at two places in the code, which are very much alike:

information = $sscanf(values0[i], "%2s%2s%2s%2s %", stringName[3], stringName[2], stringName[1], stringName[0]);


information = $sscanf(values0[i], "%2s%2s%2s%2s", stringName[3], stringName[2], stringName[1], stringName[0]);

So this code gives me two errors: $sscanf : Invalid format specifier ' at the lines you can see in the code above.

Solution

  • As Greg said in the comments:

    The trailing % should be %% if you want to match a percent sign character. See IEEE 1800-2012 Table 21-1