SystemVerilog: how to assert the signals internal to module?

Question

I am pretty new to Verilog (and of course with SystemVerilog as well). I have a RTL module to test its functionality. I was trying to use assertion to do that, instead of applying stimulus then observing it, so that my module can be reused..

So anyways, my assertion looks like following:

always @(posedge start_test)
  if (read == 1'b1 && test_type == 3'b001 && read_enable_pulse == 1'b0)
    assert property(read_test)
        $display("@%0dn read fail injection passed",$time)
      else ("@%0dn read fail injection passed",$time);

property read_test;
  @(posedge tckg) start_test |-> ##8 ((test_done == 1'b1) && (test_pass == 1'b0));
endproperty

In this case, I have a read_enable_pulse signal that is internal to a module and

I would like to see it from test bench level without binding(I don't exactly know how to either) it.

I tried to put testbenchmodule.mymodule.read_enable_pulse in a place of read_enable_pulse to go through the hierarchy but it does not seem to work..

Can anyone know how to do this?

Answer 1

Since you are already in testbenchmodule (I'm assuming this is where you're writing your assertions), try just referencing mymodule.read_enable_pulse. This should work as hierarchical paths are allowed in Verilog.

If this doesn't work (due to simulator limitations), then pretty much all simulators provide system functions that can be used to monitor internal signals. For example, Cadence has $nc_mirror and Mentor has $init_signal_spy. Have a look at your simulator's manual for more info on this.