Shift register uses too many logic elements

Question

I have implemented a shift register in VHDL. It uses "BITS" as a parameter to be able to shift a user defined number to the right. It works as intended, but takes up 164 logic elements according to the Compilation Report in Quartus II. Can anyone tell me why my code is so terrible and maybe give me a hint or two to optimize it? :) Thank you in advance.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ssi_data_align is

    port
    (
        DATA_IN      : in   std_logic_vector(31 downto 0);
        BITS         : in   std_logic_vector(4 downto 0);
        DATA_OUT     : out std_logic_vector(31 downto 0));

end entity;

architecture Behavioral of ssi_data_align is

begin

DATA_OUT <= std_logic_vector(SHIFT_RIGHT(unsigned(not DATA_IN), natural(32-(to_integer(unsigned(BITS))))));

end Behavioral;

Answer 1

If you have a lot of time, try always shifting your data_in 32 times. Then simply use the BITS as a selector to tap off on the appropriate clock cycle. You should try using clocked logic to solve the problem as it will synthesize smaller.

Maybe something like this?

process (clk)
begin
  if rising_edge(clk) then

    SHIFT_DATA <= '0' & DATA_IN(30 downto 0);

    if BITS = count then
      DATA_OUT <= SHIFT_DATA;
      count <= 0;
    else
      count <= count + 1;
    end if;
  end if;
end process;