Passing array from system verilog to VHDL

Question

I have a code in VHDL which requires an array of elements as generic. COEF_LIST : coef :=(0,0,1,1,2,-2,1,-2,1)

How do I send new set of COEF_LIST from my system verilog testbench to VHDL entity?

Generic in VHDL is same as parameter in verilog.

I declared coef as

  parameter  real COEFF[8:0] = '{0,0,1,1,2,-2,1,-2,1}; 

in system verilog.

I tried passing using (in my verilog testbench)

 vhdl_entity  #(
                 .COEF_LIST(COEFF)
               )

I get the following error

                 **.COEF_LIST(COEFF)
                                |

ncelab: *E,CFIGTC (./vhdl_entity_tb.vams,41|36): VHDL generic vhdl_entity.COEF_LIST (../views/rtl/vhdl_entity.vhd: line 34, position 14) type is not compatible with Verilog. irun: E,ELBERR: Error during elaboration (status 1), exiting.*

This doesn't work. How do I make it compatible with VHDL? I am using incisiv 13.20.008 version

Could anyone please suggest what to do?

Answer 1

Seems like you declared your COEF_LIST as an array of integers in VHDL, whereas you are trying to pass an array of reals from SystemVerilog. Try changing to:

parameter int COEFF[8:0] = '{0,0,1,1,2,-2,1,-2,1};