I get no output from the 4 bits full adder Verilog

Question

Hello guys this is my first week working with verilog. here im showing the code of a four bits adder. im just wondering why when i simulate the testbench i get an output of ZXXX0? Am i doing somthing wrong? :/

---

module adder(
input a,
input b,
input cin,
output s,
output cout
);

assign s = a ^ b ^ cin;
assign out = (a & b) | (cin & a) | (cin & b);

endmodule

---

module full_adder(p,q,ci,r);

input [3:0] p,q;    // four-bit inputs 
input ci;           // one-input input carry

output [4:0] r; // five-bit outputs 

wire [2:0] carry;   //  internal carry wires

adder fa0(p[0],q[0],ci,r[0],carry[0]);
adder fa1(p[1],q[1],carry[0],r[1],carry[1]);
adder fa2(p[2],q[2],carry[1],r[2],carry[2]);
adder fa3(p[3],q[3],carry[2],r[3],r[4]);

endmodule

---

module test_bench();

    // Inputs
    reg [3:0] p;
    reg [3:0] q;
    reg ci;

    // Outputs
    wire [4:0] r;

    // Instantiate the Unit Under Test (UUT)
    full_adder uut (
        .p(p), 
        .q(q), 
        .ci(ci), 
        .r(r)
    );

    initial begin
        // Initialize Inputs
        p = 0;
        q = 0;
        ci = 0;

        // Wait 100 ns for global reset to finish
        #100;

        // Add stimulus here
        p=4'b0011;
        q=4'b0001;
        #100 $finish;


    end

endmodule

---

Answer 1

You have typo'd one of your assignments:

assign out = (a & b) | (cin & a) | (cin & b);

should be (cout):

assign cout = (a & b) | (cin & a) | (cin & b);

This had the effect of r[4] being undriven (z) from

adder fa3(p[3],q[3],carry[2],r[3],r[4]);

and the z being driven into the cin, turns into an unknown (x) value when it hits the boolean logic:

assign s = a ^ b ^ cin;

Working example on EDAplayground.