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Why do I need to turn off IO buffers for my partially reconfigured module in Xilinx PlanAhead 14.7?


I'm using PlanAhead 14.7 and keep getting an error in the Implementation run.

This is my first time doing partial reconfiguration. I created a simple design in Project Navigator with two partially reconfigured modules. When I try implementing in PlanAhead I get an error about how part of my design had IO buffers enabled. Why do I need to disable them for my design? I still want my internal module to access the LED's and switches...


Solution

  • When you synthesize your top level design in Project Navigator you should enable the IO buffers so that your design can access the external ports, but your internal modules should not have them enabled. Normally, IO buffers are automatically turned off for internal modules, but in the case of partial reconfiguration, you are synthesizing your PR modules separately from your top level module, so you have to manually turn them off by right clicking on "Synthesize" and going to properties, click on "Xilinx specific options" and then uncheck the box next to IO Buffers. That should get rid of your error while implementing in planahead.