Port declarations without direction error

Question

In my behavioral model I keep getting this error in the file. Am I doing this correctly in Verilog? I'm getting:

Port declarations without direction are only supported in System Verilog. You must compile with the -sverilog flag to enable support for this feature.

module NSG_function
(
        input x, [1:0] q, // current_state,
        output [1:0] d // next_state
);

assign d[1] = ~x&q[0]&q[1] | x&~q[0]&q[1] | x&q[0]&~q[1];
assign d[0] = ~x | ~q[0]&q[1];

endmodule

Answer 1

Your problem is with the input q.
Though you put it on the same line as input x,, since you declare q as an array, it needs its own input declaration.

module NSG_function
(
        input x, 
        input [1:0] q, // current_state
        output [1:0] d // next_state
);

assign d[1] = ~x&q[0]&q[1] | x&~q[0]&q[1] | x&q[0]&~q[1];
assign d[0] = ~x | ~q[0]&q[1];

endmodule