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verilogsystem-verilog

verilog debugging

I don't know what is wrong with the code below. Can someone help me debug?

module iloop(z,a);
    input [31:0] a;
    output z;
    reg [4:0] i;
    reg s, z;
    initial begin
        s = 0;
        for(i=0; i<32; i=i+1)  s = s | a[i];
        z = !s;
    end
endmodule
Solution

  • Your code has an infinite loop. You have declared i as a 5-bit reg, which means its range of values is (decimal) 0 to 31. But, your for loop checks if i < 32, which is always true. Once i=31, i is incremented and rolls over to 0.

    $display is your friend. If you add it to your for loop, you will see the problem:

    for(i=0; i<32; i=i+1) begin $display(i); s = s | a[i]; end

    I think you want i<31.

    Or, maybe you want to OR all the bits of a together, using the bit-wise OR operator:

    s = |a;

    You should explain in words what you are trying to achieve.