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scalahdlchisel

Assign vec to UInt ports

if I have a io port which is io.myoutput = UInt(width = 840)

Then I have a val a = vec.fill(140){UInt(width = 6)}

How do i assign the entire a vec into the output port? I tried for loop with

for (i = 0 until 140){ 
io.myoutput(i*6+5,i*6) := a(i)}

But it gives me 

finished inference (1)
start width checking
finished width checking
started flattenning
finished flattening (2)
Lbi.scala:37: error: reassignment to Node in class TutorialExamples.Lbi
Lbi.scala:37: error: reassignment to Node in class TutorialExamples.Lbi
Lbi.scala:37: error: reassignment to Node in class TutorialExamples.Lbi

Thanks

Solution 
  • val x = Vec.fill(140){UInt(1, width=6)}
io.myoutput := x.toBits

    The "toBits" method is what you want. It flattens a Vec into its raw bits.

    I'm not sure exactly what is causing the error message, but in general, you can't really reassign to specific bits in a wire in Chisel. 

    val y = Bits(0,width=32)
y(1) := UInt(0)
y(3) := UInt(3)
etc.

    That will throw an error.