I want to make a 16to4 bit priority encoder just using 4 to 2 priority encoder? I am using verilog code, I used six 4 to 2 encoder. at the first I'v used 4 encoders and after that I put their output the input of the other tow encoders; but it doesn't work correctly at all!
module pri16to4
(input wire[15:0] in,
output wire valid,
output wire [3:0] out);
wire[1:0] pe3, pe2, pe1, pe0;
U3(in[15:12], pe3);
U2(in[11:8], pe2);
U1(in[7:4], pe1);
U0(in[3:0], pe0);
assign valid = (in != 0);
assign out = (in[15:12] != 0)? {2'b11, pe3} :
(in[11:8] != 0)? {2'b10, pe2} :
(in[7:4] != 0)? {2'b01, pe1} :
(in[3:0] != 0)? {2'b00, pe0} : 0;
endmodule
For future reference - if you've got a Verilog problem, show that you've done some work, and post the code that doesn't work. If you've got a homework problem, ask your prof.