I understand the fundamentals of verilog, but test bench just won't make sense

Question

Half Adder:

`timescale = 1ns/100ps //timescale ratio //actual HDL

module half_add(a,b,sum, carry);
  input a,b;
  output sum, carry;

  wire sum, carry;

  and(sum,a,b);
  xor(carry,a,b);
endmodule

Test bench:

module half_addTB;
reg a,b;
wire carry, sum;

//instantiation
half_add half_add1(
.a(a),.b(b),.carry(carry),.sum(sum));

 //port assignments with 10ns delays
initial begin
  #10 a = 0; b= 0;
  #10 b = 1;
  #10 a = 1;
  #10 b = 0;
end

endmodule

Code compiles fine...but when I try to simulate it, all my values are in a z state....I don't understand why..

Answer 1

You cannot drive inputs to the module from within the module.

Just instantiate your "half_add" module in another module/program (e.g. "half_add_tb") which doesn't have any inputs. then add two local regs "a" and "b", and drive those from an initial block like the one you wrote - but in the "half_add_tb" module instead.

Then just wire up the inputs "a" and "b" of the "half_add" instance to the local "a" and "b" regs.