Verilog HDL Loop Statement error: loop with non-constant loop condition must terminate

Question

I am completely new to Verilog and I have to know quite a bit of it fairly soon for a course I am taking in university. I am play around with my Altera DE2 board and quartis2 and learning the ins and outs.

I am trying to make a counter which is turned on and off by a switch. So far, the counter counts and resets based on a key press.

This is my error:

Error (10119): Verilog HDL Loop Statement error at my_first_counter_enable.v(19): 
loop with non-constant loop condition must terminate within 250 iterations
    

I understand I am being asked to provide a loop variable, but even doing so I get an error.

module my_first_counter_enable(SW,CLOCK_50,LEDR,KEY);

    input CLOCK_50;
    input [17:0] SW;
    input KEY;

   output [17:0] LEDR;

   reg [32:0] count;
   wire reset_n;
   wire enable;

   assign reset_n = KEY;
   assign enable = SW[0];
   assign LEDR = count[27:24];


   always@ (posedge CLOCK_50 or negedge reset_n) begin
       while(enable) begin
           if(!reset_n)
               count = 0;
           else
               count = count + 1;
       end
    end

endmodule

I hope someone can point out my error in my loop and allow me to continue.

Answer 1

I don't think you want to use a while loop there. How about:

   always@ (posedge CLOCK_50 or negedge reset_n) begin
           if(!reset_n)
               count <= 0;
           else if (enable)
               count <= count + 1;
    end

I also added non-blocking assignments <=, which are more appropriate for synchronous logic.