If statement and assigning wires in Verilog

Question

I am trying to figure out the basics of assigning wires based on combinational logic.

I have:

wire val;
wire x;
wire a;
wire b;

always @*
begin

if(val == 00)
 //I want to assign x = a
if(val == 01)
 //I want to assign x = b

end

where a and b are wires with values - and x is a wire going into a register.

If you can point me in the right direction to what I need to change, it would be much appreciated.

Answer 1

First thing to ask is: are you trying to use those wires as inputs? Or are you using those as connections? Second thing: Do you want a synthesizable code? And you cant assign wires inside an always block, you have to use reg

So an opinion is:

//**************************************************************************************
module(a, b, out); //You have to define an interface, and all Verilog modules starts with module 
input val[1:0]; //you have to use [] in order to indicate the length. In this case 2 bits, since you want to ask for 00;
input a;
input b;
output out;

reg x;

always @* //NOTE: You are describing combo logic, since there is no clock signal
begin

      if(val == 2'b00)
        x = a;
      else if(val == 2'b01)
        x = b;
      else 
        x = 0; //If you are describing combo logic, you have to cover ALL val cases, in                     order to evade latches

end

assign out = x; //This is how you assign values in Verilog

endmodule