Case statement in verilog

Question

I came across priority encoder design and found out a new way to do it using a case statement. The only thing that is confusing is, does a case statement give priority to cases? Example:

case(1'b1)                                
  A[3]: Y<=4'b1000;             
  A[2]: Y<=4'b0100;  
  A[1]: Y<=4'b0010;  
  A[0]: Y<=4'b0001;  
  default:Y<=4'b0000;
endcase

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Here if I give A as 1111 Y gets 1000 i.e it gives priority to the first case statement. Why is this so?

Answer 1

Yes, there is a priority, based off of the order. According to the Verilog-2001 spec, section 9.5:

The case item expressions shall be evaluated and compared in the exact order in which they are given. During the linear search, if one of the case item expressions matches the case expression given in parentheses, then the statement associated with that case item shall be executed.