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verilogverificationsystem-verilog

how to nullify register in system verilog

How do I nullify a register in SystemVerilog if I do not know the size? For example, if I have:

reg [DATA_WIDTH-1:0] data_stack;

with some parameter DATA_WIDTH given to the module. Is it possible to assign a zero to the register data_stack?

Note that it is sufficient to initialize a similar reg to zero as then I can simply perform a bitwise and between the two and nullify data_stack.

Solution

  • If I understand your question, you want to know how to generate a zero value with the same width as data_stack?

    In that case, use the replication operator:

    data_stack = {DATA_WIDTH{1'b0}};

    This generates DATA_WIDTH number of zeros.