Why are the outputs of this pseudo random number generator (LFSR) so predictable?

Question

Recently I asked here, how to generate random numbers in hardware and was told to use an LFSR. It will be random but will start repeating after a certain value.

The problem is that the random numbers generated are so predictable that the next value can be easily guessed. For example check the simulation below:

The next "random" number can be guessed by adding the previous number with a +1 of itself. Can someone please verify if this is normal and to be expected.

Here is the code I used for the LFSR:

    module LFSR(
    input clock,
    input reset,
     output [12:0] rnd 
    );

wire feedback = rnd[12] ^ rnd[3] ^ rnd[2] ^ rnd[0]; 

reg [12:0] random;

always @ (posedge clock or posedge reset)
begin
    if (reset)
        random <= 13'hF; //An LFSR cannot have an all 0 state, thus reset to FF
    else
        random <= {random[11:0], feedback}; //shift left the xor'd every posedge clock
end

assign rnd = random;

endmodule

The location of the bits to XOR are picked up from here: The table page 5

Answer 1

LFSR only generates one random bit per clock. It doesn't generate a new (in your case) 13-bit number each cycle. The other 12 bits in rnd are just the old random values, so it will not appear very random.

If you need a 13-bit random number, then you must either sample LFSR every 13 cycles, or put 13 LFSR in parallel with different seeds, and use the 13 zero bits as your random number.