I made a counter in verilog and realized it in hardware. But I am unable to explain the behaviour The code is:
module clock_test(clk_in,led,rst);
input wire clk_in;
input wire rst;
output wire [7:0] led;
reg [23:0] counter = 24'b0;
assign led = counter[23:16];
always @(posedge clk_int) begin
if(rst) begin
counter <= 0;
end
else begin
counter <= counter +1;
end
end
endmodule // clock_test
In the hardware, when I hit rst, the LEDs freeze at the point it was counting. Its not becoming exactly zero. Assert rst, and you can see some random pattern other than zero, which dont change unless I release rst.
My question is : when if(rst) begin block executes, counter is set to 0. Since leds are assigned as combo logic from counter, should'nt it reflect immediately ?
Since you have a synchronous reset the reset value would not take effect until the next clock edge after reset asserts.
When you assert reset does that also stop the clock? That would seem to be the most likely cause since otherwise your code looks correct (excepting the syntax error noted by Greg).