Verilog: Reg is not declared

Here is the declaration of the reg assignment

reg [5:0]R = {bi7 ,[15:11]RGB}; //bi7 is a parameter

but at the last line of the module i get this error where it points at the same reg assignment.

ERROR:HDLCompiler:69 - "path.v" Line 58: <R> is not declared.

Can anyone help me with this , cause my whole experience with verilog is just a book :(

Solution

In verilog, you can only assign a value to a reg in always or initial blocks. You've also got the bit range for stripping bits from you RGB bus on the wrong side of the bus name.

reg [5:0] r;
always @(RGB) begin
    r = {bi7, RGB[15:11]};
end

Note that in verilog, parameter names such as bi7 in your code, are usually defined and written in UPPER CASE to make them easy to pick out.