I have an idea about implementation reed-solomon algorithm. But in reed-solomon, an multiplier and divider is apperred a lot and need to implemented in in hardware. I googled then found Galois table for do it.
THe idea of galois table is using log-table and inverse-log-table to implement multiplier and divider (change it to Look-up-table then can use adder and subtractor).
I want to know that can I implemented it in FPGA architecture? Is it cost much resource?
I've not implemented this particular algorithm, but I recognize the type of solution you describe. Table driven logarithms are certainly a reasonable approach for FPGAs. You'll need an FPGA with a lot of internal block-RAM memory capacity.
Can this be implemented on an FPGA? Probably, at some level. Will it fit? I suggest you build a small implementation or a subset of a complete implementation. Note the resources consumed and reason through scaling up your implementation.
Check out Opencores, too. A quick google of "opencores galois table" yielded some hits.