Verilog Finite State Machine

Question

I'm trying to create a Finite state machine in verilog. The system has 4 1-bit inputs rst, clk, A, B and one output, Z.

Z is equal to 1 if either: A had same value on last two clock edges.

or B has been high (1) on every clock edge since the last rule was true.

Otherwise z=0;

I don't have the tools to simulate my attempt atm. So I'm wondering if this is the correct method and if i'm on the right track?

module StateMachine( R, A, B, clk, Z);
   input R, A, B, clk;
   output reg Z;

   reg ATemp;
   reg state;

   always @ (posedge clk or A)
      if (A == 1'b1) 
      /////////////////
      begin
         if (ATemp == 1'b1) state <= 1'b1; 
         else ATemp <= A;
       end
       ////////////////
       else
       ////////////
       begin
          if (ATemp == 1'b0) state <= 1'b1;
          else ATemp <= A;
       end


   always @ (state)
      case(state)
         1'b0: Z=0;
         1'b1: Z=1;

         default: Z=0;
      endcase

endmodule

Answer 1

You can use the following tools:

GHDL is an open-source simulator for the VHDL language ( User Guide )

Additionally these are the most popular simulation tools:

• Active-HDL
• Altera ModelSIM
• Riviera pro ISE simulator

Further resources:

There is also the stackexchange electronics community and codereview.

• Overmapped: a forum on VHDL topics

Additionally, heed the C to HDL compiler tool

(.. I doubt many can review your code in 3 minutes, nor would I want them too )