module A (
output A_OPORT_1
);
endmodule
module B (
input B_IPORT_1
);
endmodule
module TestBench;
wire A_to_B;
A A_inst (
.A_OPORT_1 (A_to_B)
);
B B_inst (
.B_IPORT_1 (A_to_B)
);
endmodule
Here basically output port A:A_inst:A_OPORT_1 is connected to B:B_inst:B_IPORT_1
How can I retrieve that information using a verilog PLI? Example appreciated.
I have some code that gets a port and retrieves the highconn and is able to get the wire/net A_to_B.
However I am not able to find out what ports are connected to A_To_B using vpiPortInst. I get an iterator that is null.
vpiHandle high = vpi_handle(vpiHighConn, port);
vpi_printf(" High conndata type is %s\n",
vpi_get_str(vpiType, high));
vpi_printf(" High conndata Net type is %s\n",
vpi_get_str(vpiNetType, high));
vpi_printf(" High conndata Name is %s\n",
vpi_get_str(vpiFullName, high));
vpiHandle iter = vpi_iterate(vpiPortInst,high);
vpiHandle p2ref;
if (iter == NULL)
{
vpi_printf(" Port Iterator is null\n");
}
O/P:
High conndata type is vpiNet
High conndata Net type is vpiWire
High conndata Name is $unit::A_to_B
Port Iterator is null
The above code works. As toolic pointed out the two ports have to be connected.
Now this works and I'm able to print out the fan outs.