How to disable XST FF/Latch trimming or hide warnings about it

Can anyone explain to me how can I disable XST FF/Latch trimming ? In this particular example, I know why trimmings are occurring (I don't want to go into details), but they are occurring on very large std_logic_vector (two vectors with 128 bits).

That said, I get many warnings and can't see if anything else is wrong (that I would care about). So I would like to hide warnings or disable FF/Latch trimming. Is that possible ?

Thanks !

Solution

In ISE you can hide particular warnings from the message window IIRC. I think right-clicking the message might be the way.

Personally, I tend to use a pure command-line flow - including a script which "edits out" the messages I have defined as being "uninteresting" or "supposed to happen" via a set of regexps in a side-file. Of course, then I have to validate the regexps :)

How to implement HDMI pass-through on XILINX FPGA (Artix-7)
Petalinux 2021.1 doesn't recognize the machine name for ZCU106
NEC Infrared Transmission Protocol in C lanc on Xilinx
Armv7 MMU on the ZYNQ-7000 not starting the virtualization
Xilinx Vivado 2023 IP block design issue: Unable to connect output of RTL module to AXI GPIO output that is connected to LED
Where to force xilinx ISE to use block-rams?
Is CRC Calculation Faster on Xilinx Alveo U280 FPGA Using a Custom Algorithm or a Lookup Table?
How to implement pipelined floating point accumulation in II=1 in Vitis/Vivado HLS?
Timing simulation in Vivado giving an error
Is it possible to tie ports high always high outside of top module?
How to fix [Common 17-1293] error in Xilinx Vivado?
How to initialize contents of inferred Block RAM (BRAM) in Verilog
Implementing hardware that divides an 8 bit number by 3 (11) in binary
Can SYSCLK be included in FPGA Xilinx vivado testbenches?
Isim not running
how to add python in xilinx vitis
Timing closure problems in FIFO
Xilinx Vivado schematic for if else statements
difference between Xilinx solarflare scaleout onlod, solarflare onload, and solarflare TCPDirect?
Inferring a True Dual Port RAM (Xilinx and Intel compatible) in Verilog
'case item is unreachable' in Vivado synthesis process
Why does the Inferred Latch error occur during the synthesis process?
What is the granularity of the AXI-ACE protocol?
Restricting Verilog parameters
Vitis HLS Pointer to Pointer is not supported for variable when initializing struct array
Vitis PetaLinux build cant fetch required files while building an application project
Address of a struct used to set MSI Base address, how does it work? (in Xilinx PCIe RC driver)
How To Convert .bit file to .bin
of_node_name_eq for device tree node label
using xilinx cores in modelsim via .do file