verilog Examples and Free Source Code

Binary - BCD convertor works in sim, but does not work on FPGA...

verilog fpga synthesis register-transfer-level

Does the SystemVerilog standard allows mixing with Verilog files?...

verilog system-verilog

How to concatenate number (1'b1) and `define in a single statement...

concatenation verilog

Why am I not getting output after pass through design in testbench module driver and monitor?...

verilog system-verilog

Implicit net-type declaration and `default_nettype...

verilog system-verilog

Is there a way to condition on a type?...

verilog system-verilog parameterized-types

Error (10170): HDL syntax errors in Quartus (HDL)...

verilog system-verilog hdl quartus

Error opening .vcd file. No such file or directory...

verilog iverilog gtkwave

Ternary operation not working with unary operation...

verilog system-verilog

Reading parameter array through VPI...

arrays verilog system-verilog verilator vpi

Unexpected results in fixed-point conversion in Verilog...

verilog system-verilog iverilog

Trying to change Hexadecimal display to Signed Decimal in VCD...

verilog

How to reuse the genvar in Verilog?...

verilog system-verilog

How to define a module with a parameter in Verilog?...

verilog system-verilog

System Verilog Scheduler...

verilog system-verilog

Generate custom waveform in verilog...

verilog

Accessing Verilog genvar generated instances in simulation code...

simulation verilog hdl synthesis

Extend a value with ones in SystemVerilog...

verilog system-verilog

reg qb; cannot be driven by primitives or continuous assignment...

verilog hdl iverilog

"Invalid Module Instantiation" Error in Mealy sequence detector - Verilog...

verilog

Shift Register Design using Structural Verilog outputs X...

verilog gorilla flip-flop shift-register

How to write a shift register in a recursive way...

verilog shift-register

Shift Registers Verilog...

verilog vlsi shift-register

Serial output shift register indetermination...

verilog system-verilog shift-register

ShiftRegister Verilog HDL Output giving xxxxxxx...

verilog system-verilog hdl shift-register

Declaring variables in Verilog for loop...

verilog system-verilog fpga

Use of inout in task using fork-join_none...

verilog system-verilog

How to initialize the queue of queue?...

verilog system-verilog verification

Testing multiple configurations of parameterizable modules in a Verilog testbench...

verilog system-verilog test-bench iverilog

Function to convert logic vector into string...

arrays verilog system-verilog