verilog Examples and Free Source Code

Issue with driving an LED matrix using an FPGA (Verilog)...

verilog fpga hdl led

How to write a part select expression using shift operator in system verilog?...

verilog system-verilog

How to fix multiple driver and combinational loop problems?...

verilog system-verilog hdl register-transfer-level

FSM stuck at one state...

verilog system-verilog fsm

Signed multiplication: multiplying numbers of different sizes?...

verilog system-verilog

verilog LRM 23.3.3.1 connecting output to output...

verilog system-verilog iverilog

Does Verilog support short circuit evaluation?...

verilog

Why does APB testbench not send data into the prdata register?...

verilog system-verilog uvm test-bench edaplayground

Bidirectional simulation of nmos/pmos in Verilog...

verilog simulation vlsi

Anonymous struct export to top...

struct verilog system-verilog register-transfer-level

How to define an enum type and include it in multiple modules?...

verilog system-verilog

Verilog parsing between logical and bitwise not (!/~)...

verilog system-verilog

Empty statement in verilog that requires a semicolon?...

verilog

Cannot get yosys to infer BRAM...

verilog yosys ice40

Why the test bench module doesn't work as intended?...

verilog system-verilog test-bench

Simulation error in modelsim ACTEL6.6d: Illegal output or inout port connection...

simulation verilog modelsim

What is the reason for this error in ModelSim for my Verilog code? (string_literal.v(3): near "...

verilog modelsim

Cadence IUS simulator options...

verilog system-verilog cadence

Usage of 'begin/end' in design modules...

verilog system-verilog

How to fix this part-select error? Illegal operand for constant expression...

verilog system-verilog

How to implement HDMI pass-through on XILINX FPGA (Artix-7)...

verilog xilinx hdmi pass-through

Find minimum in array of numbers using Verilog for Priority Queue implementation...

arrays comparison verilog priority-queue system-verilog

LED Sequence on Basys3 with Verilog...

verilog system-verilog fpga vivado

Is it possible to create task within interface for specific modport?...

verilog system-verilog

Formal verification of synchronous FIFO with failing SystemVerilog assertion...

verilog system-verilog formal-verification system-verilog-assertions

Connecting output of 4-bit counter to Hex to 7-Seg decoder and creating testbench...

verilog system-verilog fpga

Weird Behavior of buffers in modelsim simulation...

verilog delay system-verilog modelsim test-bench

Why the memory content is not read? - verilog digital system design...

memory verilog system digital iverilog

I see undefined output sequences reading a memory in simulation...

memory verilog simulation test-bench iverilog

Vivado behavioral simulation results differ on different PCs, but synthesis results are the same...

verilog system-verilog vivado