verilog Examples and Free Source Code

T flip-flop using dataflow model...

verilog system-verilog flip-flop

Use if-generate structure to define two variations of a function, and call that function in the same...

verilog system-verilog

SystemVerilog inheritance, aggregated classes and parent function call...

oop verilog system-verilog fpga modelsim

Verilog module instance named after different module type...

verilog

String triple quotes not getting accepted by simulators...

verilog system-verilog

Verilog always @(posedge clk) dosent work...

verilog system-verilog modelsim

Testbench for writing to the file in Verilog...

verilog vlsi

SystemVerilog not reading data correctly...

verilog system-verilog modelsim digital-design

How can I schedule multiple inputs into an instantiated SystemVerilog module?...

verilog system-verilog hdl register-transfer-level

Icarus Verilog Syntax error "I give up" for NAND gate...

verilog iverilog

How to specify AUTO_TEMPLATE wild card for inputs and outputs separately?...

emacs verilog

localparam for case values with don't cares. Is 1'b? legal?...

verilog priority-queue

Verilog how does assign statement work with a conditional operator?...

verilog

SystemVerilog parameter override unsigned...

parameters verilog system-verilog

Icarus verilog dump memory array ($dumpvars)...

arrays memory verilog dump iverilog

Assign a SV port...

verilog system-verilog register-transfer-level

How do I install GTKWave on Windows?...

gtk verilog vhdl simulator gtkwave

Missing data while shuffling...

verilog

Register increments twice within a non blocking always...

verilog digital digital-design

Can Verilog functions access variables declared outside the function block?...

function variables module scope verilog

How can I calculate a generate loop control value from a module parameter?...

verilog

Why is "Set as Top-Level Entity" grayed out in quartus?...

verilog system-verilog hdl quartus

How to fix [Common 17-1293] error in Xilinx Vivado?...

verilog xilinx vivado

How to initialize contents of inferred Block RAM (BRAM) in Verilog...

verilog fpga xilinx vivado

'Illegal output or inout port' error when trying to simulate counter...

verilog system-verilog test-bench

Assignment to two different wires with a bit and its complement yields the same value...

architecture verilog

How to convert Signed Binary to Integer in Verilog?...

verilog

Rounding down the absolute value of signed fixed point numbers in Verilog...

verilog rounding fixed-point

Formal verification of state machine with SymbiYosys not giving expected results...