synthesis Examples and Free Source Code

How do you write a parameterized delay register?...

verilog hdl vivado synthesis

Multiple processes driving an array of records...

arrays vhdl record multiprocess synthesis

Error: [VRFC 10-2951] 'WIDTH_DIFF' is not a constant...

verilog fpga vivado synthesis

Why Yosys synthesis the sequential statement to constant...

synthesis yosys

Synthesizable VHDL recursion, Vivado: simulator has terminated in an unexpected manner...

vhdl simulation vivado synthesis

Verilog error "continuous assignment output must be a net"...

verilog synthesis

Quartus crashes when trying to synthesize RAM in Verilog...

verilog fpga quartus synthesis

Synthesized for loop in always_ff block...

function for-loop verilog system-verilog synthesis

VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)?...

integer logic width vhdl synthesis

Linking Error cmake - Using CodeSynthesis XSD in cmake...

c++cmake synthesis

Error when trying to synthesize verilog code...

verilog synthesis

What is "??" in Verilog casez?...

verilog synthesis

Assigning entire array in verilog...

arrays verilog assignment-operator synthesis

How to access the AST for constraints in the input sygus file in CVC4 tool...

c++smt synthesis cvc4

Addition/Substraction Optimization in Yosys...

synthesis yosys

Prevent sharing of adder logic...

vhdl quartus synthesis

SV: Error llegal combination of procedural drivers...

driver system-verilog synthesis

How do I design Serial to Parallel Buffer in Verilog only using clocks?...

deserialization verilog fpga synthesis register-transfer-level

Synthesis for statements of wait, infinite loop, while loop, and for loop in VHDL...

loops vhdl wait synthesis

Extra variable assignment in VHDL code makes it not work and get error "can't infer registe...

vhdl quartus synthesis

Verilog cannot synthesize when using external counter inside generate block...

verilog vivado synthesis generate

Are multiple non-nested if statements inside a VHDL process a bad practice?...

if-statement vhdl synthesis

Verilog for loop failed to synthesis using oasys...

for-loop verilog synthesis hardware

Is $readmem synthesizable in Verilog?...

verilog synthesis

VHDL synthesis warning FF/Latch has a constant value of 0...

warnings vhdl synthesis

CVC4 cannot open file in SMT2 format...

file synthesis cvc4

Big multiplexer with for loop in Verilog...

for-loop switch-statement verilog synthesis

Verilog sequence of non blocking assignments...

verilog synthesis

How can I force vivado to use dsp blocks for all arithmetic operations...

verilog signal-processing fpga vivado synthesis

Why do incomplete if statements create latches during synthesis in VHDL?...

vhdl synthesis digital flip-flop