synthesis Examples and Free Source Code

Binary - BCD convertor works in sim, but does not work on FPGA...

verilog fpga synthesis register-transfer-level

Accessing Verilog genvar generated instances in simulation code...

simulation verilog hdl synthesis

Mismatch between behavioral simulation and post-synthesis functional simulation in vivado...

vhdl fpga vivado synthesis

Synthesis ERROR: [Synth 8-27] else clause after check for clock not supported...

if-statement vhdl synthesis

How to reproduce C64-like sounds?...

audio synthesis c64

Xilinx Vivado schematic for if else statements...

if-statement system-verilog xilinx vivado synthesis

When designing digital circuits, which is more power efficient, an if-statement or a multiplication ...

verilog synthesis

What is the basis for setting parameter values in the sdc file?...

synthesis

How to know whether a Verilog code can be synthesized?...

verilog synthesis

Vivado linter: inferred latch for signal 'out_reg'...

verilog vivado synthesis

D-flip flop with 2 reset: synthesis error...

verilog synthesis register-transfer-level

Flip flop reset with ternary operator instead of if-else statement...

verilog system-verilog synthesis register-transfer-level

On left-hand side of assignment must have a variable data type...

verilog variable-assignment system-verilog quartus synthesis

How do I get rid of sensitivity list warning when synthesizing Verilog code?...

verilog system-verilog synthesis

Setting values in an initial block in Verilog...

verilog system-verilog synthesis

Vivado: Mismatch between behavioral simulation and post-synthesis functional simulation...

vhdl synthesis

Vivado Not Creating Schematic after Synthesis...

verilog vivado synthesis

Verilog: Simulation and Hardware Implementation differ in one state behaviour...

verilog simulation state-machine synthesis

Variable output stream delay attempt not working...

verilog vivado synthesis

Convert Mat to Array/Vector in OpenCV...

c++arrays opencv vector synthesis

Start up behavior of moving average filter is different between pre and post synthesis functional si...

verilog simulation system-verilog fpga synthesis

Verilog high impedance inout synthesis...

verilog synthesis inout

Struggle to program an LFO...

c sdl synthesis

Is it possible to see if vivado inferred blockram?...

vivado synthesis

How to invert a bit of a packed array...

verilog system-verilog synthesis register-transfer-level

Is indexing into an array with a signal synthesizable in verilog?...

verilog synthesis

Are SystemVerilog packed arrays row or column major for literal assignment?...

arrays system-verilog synthesis

Logic synthesis from an arbitary piece of code...

logic vhdl verilog synthesis

Sound synthesis with C#...

c#.net audio signals synthesis

mixed VHDL & Verilog designs: which free simulation and/or synthesis tools?...

vhdl simulation verilog synthesis