quartus Examples and Free Source Code

How do I concatenate parameters and integers?...

verilog system-verilog quartus intel-fpga

Output 'X' instead of '1' or '0' in VHDL...

vhdl quartus intel-fpga

"Serial Loader Device is missing" during Convert Programming File with Quartus Prime...

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ModelSim Simulation Stops Earlier than Expected...

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How to connect module to module in Verilog?...

verilog system-verilog fpga quartus intel-fpga

How to correctly calculate the frequency of the device in Timing Analyzer, Intel Quartus...

verilog system-verilog timing quartus intel-fpga

Verilog - output exuals to XXXXXXXX...

verilog fpga quartus intel-fpga

How to make a constant binary number adapt to a Generic statement in VHDL...

vhdl quartus

ModelSim-Altera error...

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How can I prevent that DSP blocks are synthesized away if they are not connected to a top level outp...

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How do I load an FPGA's Registers with Data?...

verilog quartus intel-fpga

How can I stop quartus from jumping to the 'compilation report'?...

quartus

Altera Quartus Error (12007): Top-level design entity "alt_ex_1" is undefined...

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How to drive outputs in Verilog...

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How to get rid of truncate warnings when initializing a parameter-sized array?...

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Type of identifier does not agree with its usage as "boolean" type - VHDL in Quartus...

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I wrote this code in Verilog and there are no error messages, but it doesn't work...

verilog system-verilog hdl modelsim quartus

Swapping 2 parameters in always_ff @...

verilog system-verilog quartus

VHDL count and shift...

vhdl quartus

How do I make Quartus II compile faster...

vhdl quartus

Changing triggering edge depending on clock polarity signal...

vhdl clock edges quartus

Verilog HDL syntax error at practice.v(7) near text "or"; expecting ")"...

syntax-error verilog quartus

Capturing the right posedge clock in Quartus waveform...

verilog quartus test-bench digital-logic register-transfer-level

The clock speed is two times faster when the clock duty cycle is 50%...

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Unknown values (X) in simulation of parking lot gate...

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Designing T-Flipflop on Quartus...

vhdl quartus

In Intel Quartus, can I initialize RAM using a string parameter?...

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Beginner's Question on Compiling Verilog in Quartus...

verilog quartus

How do you appropriately multiply std_logic:vector in VHDL?...

vhdl quartus intel-fpga

Which files or folders should be in .gitignore in Quartus Prime 18.1 Lite (Verilog) project?...

git gitignore quartus