Initializing IO with a bundle in Chisel 3.5...

Chisel how to test only one package...

Chisel memory write mask...

How to find the number of PLIC contexts?...

Scala Chisel. BlackBox with 2-d verilog ports...

How to initial a 2 Dimensions matrix with independent number of rows and columns in Scala?...

Calling Dsptools produces a Chisel runtime error...

what is the idiomatic way to update *part* of a memory element in FIRRTL? this comes up when updatin...

Why is this local var not set correctly according to ChiselTest...

How to assign data to a register in chisel?...

Chisel test - internal signals...

How to correctly pass implicit parameters to a module?...

I can't import the class whose path is IDEA's source root file...

Timescale missing on the module as other modules have it Verilator error...

False "Combinational loop detected"...

Adding an MMIO peripheral to Rocket-chip as a submodule...

How does a missing boolean operator still compile?...

Developing Generic AXI4 Peripheral with Chisel...

How to import packages into another package(or files in the same package) using "import" e...

RegInit initializes value only on reset...

problem compiling a switch case statement in chisel...

Conditional Module instantiation in Chisel...

Chisel queue module test results don't match what i expected...

In chisel 3, how to initialize memory test code with text file...

Formal verification with Chisel...

In chisel, How to generate serval Module with different parameter?...

How to use a vector as input in Chisel...

What does `vec type 'AnonymousBundle(IO io in <module>)' must be a Chisel type, not ha...

Does chisel3's printf generate terminal output when simulating the emitted verilog?...

Is it possible to flip an Analog value in Chisel?...