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constraintsxilinxspartan

Spartan 3 Starter Kit Constraints File

I am not sure if this is the right stack exchange website to post this on, but if it isn't please move it to the appropriate one.

I am facing a small problem in writing my constraints file for the spartan 3 starter kit.

I have read the documentation provided by Xilinx (the manufacturer) and ive been searching online for a few weeks without any luck.

What i am trying to do is link my Netlist interface to any of the 3 40-pin-headers on the board. (See image below)

enter image description here

Usually its very simple, if say i want to interface a button or a led on the board, i just read the connection name on the board, for example one of the buttons is M13 and write in the UCF file something like this :

NET "BTN0"       LOC = "M13";

As you can see on the image the headers are named A1, A2 and B1 on the board, but oddly enough, none of the following worked :

NET "TestOutputLine"       LOC = "A1(0)"; -- The (0) is to reference a single line on an array
NET "TestOutputBus"       LOC = "A1"; -- The bus is of equal dimension of A1 (which is 40)

The errors i got meant that either the target (specified by LOC) does not exist or that the assignment is invalid.

I hope you have some ideas for me. Thanks in advance

EDIT : Here is the output from ISE :

ConstraintSystem:59 - Constraint <NET "TestOutputBus" LOC = "A1";>
[circuit.ucf(12)]: NET "TestOutputBus" not found.  Please verify that:
   1. The specified design element actually exists in the original design.

But i am pretty sure that TestOutputBus exists, as a matter of fact there is nothing else in my design right now, and the correct top level unit is being used.

enter image description here

EDIT2 : I updated my UCF file, right now it's like this :

NET "TestOutputBus(0)" LOC = "A1(0)";
NET "TestOutputBus(1)" LOC = "A1(1)";

But i get a different error now in mapping :

MapLib:30 - LOC constraint A1:0 on TestOutputBus<0> is invalid: No such
   site on the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.
MapLib:30 - LOC constraint A1:1 on TestOutputBus<1> is invalid: No such
   site on the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.

Solution :

In order to get the pins 5 and 6 mapped to TestOutputBus(0) and TestOutputBus(1) respectively what i had to use was this :

NET "TestOutputBus(0)" LOC = "N7"; -- A1 pin 5
NET "TestOutputBus(1)" LOC = "L5"; -- A1 pin 6

Note that pins 0 are not mappable thats why i used pins 5 and 6, here are the tables that show the mappable pins for all headers and their LOCs.

enter image description here enter image description here enter image description here

Solution

  • As it turns out, there is an address for each usable pin of each header of the FPGA.

    The datasheet (http://forums.xilinx.com/xlnx/attachments/xlnx/Spartan/3411/1/S3BOARD_RM.pdf) was helpful especially pages 49 - 51