VHDL Compare not working in hardware but works in simulation

Question

Hi guys I have the following VHDL which isn't doing what it suppose to in hardware but it does work in simulation. Basically I have a counter and depending on the count I want certain data to be output I implemented the mux as following:

write_data  <=  
('1' & '0' & "1111"                                                              )  when (data_cnt_r < 1)  else             
('0' & '0' & "1111"                                                              ) when (data_cnt_r >= 1 and data_cnt_r < 2 ) else
('0' & '0' & "0000"                                                              ) when (data_cnt_r >= 2 and data_cnt_r < 3 ) else  
('0' & '0' & data_reg                                                        ) when (data_cnt_r >= 3  and data_cnt_r < 1027 ) else
('0' & '1' & CRC16_o(63) & CRC16_o(47) & CRC16_o(31) & CRC16_o(15) ) when (data_cnt_r >= 1027  and data_cnt_r < 1043 ) else 
('0' & '0' & "1111");   

The problem I am getting is that when the count is 1043 I see the CRC output instead of seeing "1111" for the last line in the code. In the simulation it works like I would expect. Is there a better way to write this? Any ideas why the discrepancy?

*EDIT More details as requested:

I'm using

   use IEEE.STD_LOGIC_UNSIGNED.ALL; 

data_cnt is a free runnig counter, everything is std_logic_vector or std_logic

    signal data_cnt_r       : std_logic_vector(11 downto 0); -- 12 bit counter

write_data goes to a BUFIO and it is also a standard logic vector

Answer 1

What is happening near your other transitions? (1027, 3, 2, 1) is this in a process block or is it asynch? is data_cnt_r an unsigned? What about data_reg and CRC values? I assume both std_logic_vectors?

We need a little more context

you could try explicitly adding a transition to see if it helps ala:

('0' & '1' & CRC_stor)  when (data_cnt_r >= 1027 and data_cnt_r < 1043 ) else 
('0' & '0' & "1111"  )  when (data_cnt_r = 1043) else
('0' & '0' & "1111"  );

if this is actually in a clocked process block you might see the CRC values in write_data a clock cycle later but then you would also see this problem around your other transitions (they would all update a cycle behind data_cnt_r)

You might be getting unexpected logical errors if its in an unclocked process block

Also this is a little easier to read.

CRC_stor <= CRC16_o(63) & CRC16_o(47) & CRC16_o(31) & CRC16_o(15)

write_data  <=  
   ('1' & '0' & "1111"  )  when (data_cnt_r = 0) else             
   ('0' & '0' & "1111"  )  when (data_cnt_r = 1) else
   ('0' & '0' & "0000"  )  when (data_cnt_r = 2) else  
   ('0' & '0' & data_reg)  when (data_cnt_r >= 3    and data_cnt_r < 1027 ) else
   ('0' & '1' & CRC_stor)  when (data_cnt_r >= 1027 and data_cnt_r < 1043 ) else 
   ('0' & '0' & "1111"  );