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vhdlfixed-point

fixed point conversion from a real variable in vhdl

I have the following code snippet in vhdl:

signal s: signed(31 downto 0);
s <= to_signed(to_sfixed(1.2,8,-23),32);

Now I am expecting the fixed point version of 1.2 to be available in the signal 's'.

But it always neglects the fraction part. The 's' just contains the decimal part(here "1").

What am I missing here?

Solution

  • If you just want to reinterpret the bits from the sfixed to as signed type, just use a simple type conversion:

    signal s: signed(31 downto 0);
...
s <= signed(to_sfixed(1.2,8,-23));