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Module instantiation when number of ports are dynamic

I'm trying to do a module instantiation. But, the problem is number of ports in my module(x) could change based on a parameter. I'm using this parameter to generate this module(x) as block design and then exporting a wrapper in Vivado.

If my parameter (NUM_INSTANCES) = 2, my instantiation would look something like this:

x inst(
.a (something),
.b (something)

If its 3:

x inst(
.a (something),
.b (something),
.c (something)

So because of this, I'll have to keep different .sv files for each parameter. Is there any way to do this on the go ? Like having a loop inside instantiation ?

I've tried adding loops inside instantiation. Looks like it doesn't work. Something like this:

x inst(
 for(int i=0;i<NUM_INSTANCES;i++) begin
  .a[i] (something)
Solution

  • As you see, you can not simply change the number of ports based on a parameter.

    However, you could use a port declared as an array where the number of ports is set by a parameter. Refer to IEEE Std 1800-2017, section 23.3.3.5 Unpacked array ports and arrays of instances.

    module x #(parameter N=3) (input [3:0] a [N]);

    Alternately, you could always use your favorite software language to automatically generate whatever Verilog code you need, then include the generated code.