Where do I start to make a bare-metal os?
How would I make a riscv64 bare-metal os? What I mean is like a OS that can just act as a text editor so you can type and use backspace, shift, and caps-lock
I'm not asking for someone to do it for me but for someone to tell me where to start and what resources to use. I also know this will take a long time but I want to work on it.
How would I make a riscv64 bare-metal os?
You have to decide the features that define a simple OS.
For me, that is threads and operating system service calls in a shared single address space system.
My service calls allow at least:
Implementing such requires: a programming model for invoking the service calls, and an interrupt service routine (ISR) that handles these system calls & external interrupts for keypress and console ready.
My programming model uses csrrw zero, %arg, zero to accomplish a numbered trap (%arg is the number) for user-mode code to invoke operating system services. Executed in user-mode, this instruction will fault (cause an exception) switching to privileged mode and invoking the kernel ISR to handle the request.
My system maintains csr uscratch (a privileged register) as a pointer to the context block for what ever is running (but is self-initializing in that if uscratch is 0 then it will assign a context block). The system maintains uscratch pointing to a context block for a user-thread or an element of the interrupt context block stack. Each user-thread context block points to the next level context block to use in the case of an interrupt (which is the level 0 of the stack), and each interrupt context block points to the next context block in that stack, allowing for nested interrupts (for slow & fast devices).
The interrupt service routine can service an interrupt and decide what thread to resume. If the service call was a user-mode read request and there is a key press ready in that thread's keyboard buffer, then that thread can be resumed. However, if there is no key in that thread's keyboard buffer, then another thread can be resumed instead. (The main thread turns itself into an idle thread when it is done setting up the system, so there's always a thread that can be resumed.) The ISR is divided into two sections: quick service, and full service. Quick service suspends a thread only enough to service the interrupt and resume that same thread, whereas full service suspends the thread such that another thread can be resumed.
(Further, if the interrupt was external and nested, then the only option is to resume the interrupted service call.)
The ISR also maintains a keypress buffer and console output buffer for each thread.
It is implemented using RARS, as that has sufficient support for user-mode code and an m-mode privileged exception handler (ISR).
More features can be built, such as setting up timers for time slicing and providing timer services.