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verilog

Building a vector starting with 1 and followed by zeros using vector concatenation and replication

I have the following Verilog code that is throwing an error that I can't quite manage to figure out:

module error #(parameter WIDTH = 8);
  reg [WIDTH - 1:0] v;
  
  initial begin
    v <= {1'b1, {WIDTH - 1}{1'b0}};
  end
  
endmodule

I basically want v to be a vector that starts with a 1 and is followed by a bunch of 0. For example, if the parameter WIDTH is 8, I want to obtain the vector 10000000.

The code above is giving me an error that says 'expecting a right brace' and 'expecting a semicolon'. I think I just don't quite understand the syntax for vector replication and/or concatenation. I tried a bunch of combinations for the syntax, like using () instead of {}, adding extra {} to the 1, using the b syntax or not using it, without any success.

The parameter, as well as the usage of the concatenation syntax is necessary for my actual design, the code above being just a small module to showcase the issue, so ideally I would like to find out why this error occurs and what should I change in my syntax to make this work.

Solution

  • The braces are not placed properly.

    Change:

    v <= {1'b1, {WIDTH - 1}{1'b0}};

    to:

    v <= {1'b1, {(WIDTH - 1){1'b0}}};

    Refer to IEEE Std 1800-2017, section 11.4.12.1 Replication operator

    The parentheses are not required, but I think they make the code easier to understand.