Search code examples
verilog

Define constant from expression

I know I can define constants in Verilog very statically:

`define FETCH_1 0
`define FETCH_2 1
`define ADD_1 2
...
`define PUSH_2 134

Is it possible to create a constant from an expression, e.g. something similar to that (Java syntax):

public static final int FETCH_1 = 0
public static final int FETCH_2 = FETCH_1 + 1;
public static final int ADD_1 = FETCH_2 + 1;
...
public static final int PUSH_2 = PUSH_1 + 1;

so it is easy to later add a constant in the middle without having to change all following constants? Or should I use a different language that creates a constants file with define statements?

Solution

  • Yes, it is possible to use constants in expressions when defining other constants.

    `define ADD_1 `FETCH_2 + 1

    When using `define macros, you need to use the ` prefix when using the macro.

    This is also possible with constants declared as parameter:

    parameter FETCH_1 = 0;
parameter FETCH_2 = FETCH_1 + 1;
parameter ADD_1   = FETCH_2 + 1;

    Refer to IEEE Std 1800-2017, section 6.20 Constants