Calculate package latency when DPDK cycles overflow

the following code used to calculate package latency:

TICK_PER_SECOND = rte_get_tsc_hz();

us_cycles = TICK_PER_SECOND / 1000 000;

register uint64_t received_cycles = rte_get_timer_cycles();

//sent_cycles will be recorded at somewhere
uint64_t latency = received_cycles > sent_cycles ? received_cycles - sent_cycles :
                       0xffffffffffffffff - sent_cycles + received_cycles;

uint64_t latency_us = latency / us_cycles

but sometimes latency_us will be a huge number like: 8384883669867977 us

is there some error calculation when the code handle cpu's cycles overflow? should replace 0xffffffffffffffff with UINT64_MAX?

latency_us should be a normal value.

Solution

rte_get_timer_cycles() (uint64_t) has incremental values but surely it will overflow after some time (around every 2 hours depending on your cpu speed) and start from 0 when it reaches the value near UINT64_MAX. so,

uint64_t latency = received_cycles > sent_cycles ? received_cycles - sent_cycles : 
UINT64_MAX - sent_cycles + received_cycles;

should do just fine as you guessed