Using FPGAs, I am trying to bring at least some data to physical contact, but nothing comes to contact from the word at all. I use Xlinix.
Here's what the code looks like:
the main module that accesses the translator and which transmits generates data:
module main
(
input wire clkin, // Clock signal
input wire reset, // Reset signal
output wire DI, // data
output wire DE, // The ready bit
output wire uart_tx
);
IBUFG clkin1_buf
(.O (clk/*clkin1*/),
.I (clkin));
UART_Transmitter uart_transmitter (
.clk(clk),
.reset(reset),
.data_ready(ready_tx),
.data(date_tx),
.tx(uart_tx)
);
assign ready_tx = 1'b1; // We always set data_ready to a logical unit
assign DI = uart_tx;
assign DE = ready_tx;
endmodule
the data generation module from where we get either some value or a constant unit:
module UART_Transmitter (
input wire clk, // Clock signal
input wire reset, // Reset signal
input wire data_ready, // Data ready signal for transmission
input wire [7:0] data, // Data to be transmitted
output reg tx // UART output signal
);
reg [3:0] bit_counter = 4'd0; // Bit counter
reg [10:0] shift_reg = 11'b0; // Shift register for data
always @(posedge clk) begin
if (reset) begin
bit_counter <= 4'd0; // Reset the bit counter
shift_reg <= 11'b0; // Reset shift register
tx <= 1'b1; // Setting the logical unit on the transmission line
end else if (data_ready) begin
case (bit_counter)
4'd0: begin // Start bit
shift_reg <= {1'b0, data}; // Forming the start bit and data
tx <= 1'b0; // Setting a logical zero on the transmission line
bit_counter <= bit_counter + 1; // Bit counter increment
end
4'd9: begin // Stop bit
tx <= 1'b1; // Setting the logical unit on the transmission line (stop bit)
bit_counter <= 4'd0; // Resetting the bit counter for the next byte
end
default: begin // Data
shift_reg <= {shift_reg[9:0], 1'b0}; // Data shift for transmission
tx <= shift_reg[10]; // Sending data bits
bit_counter <= bit_counter + 1; // Bit counter increment
end
endcase
end else begin
tx <= 1'b1; // Setting the logical unit on the transmission line if the data is not ready
end
end
endmodule
My main guesses are in the logic of the data transfer of the modules, since all the logic in the modules themselves seems to be in order, but no signal comes at all.
Signal date_tx in module main is undriven/unconnected. This is the parallel data input to the UART_Transmitter module.
The UART_Transmitter // Data to be transmitted signal is unconnected.
This signal must be driven with parallel data for the UART_Transmitter to send anything.
Basically the tx uart has no data input.
No input means no output.
UART_Transmitter uart_transmitter (
.clk(clk),
.reset(reset),
.data_ready(ready_tx),
.data(date_tx), // <- This signal is undriven in the posted code
.tx(uart_tx)
);
When this design is built in a Xilinx synthesis workflow, the tools will optimize/remove the uart logic because nothing is connected to the input. That is what the synthesis tools do; if something is not connected optimize/remove it.
Recommend verifying the design using simulation (in this case verify that the tx uart send data) in a testbench prior to deploying to the lab.
Typical tx uart designs use a dual port fifo to hold data waiting to be transmitted on a serial transmission line. Data is loaded into the filo by a computing host on one side, and the fifo get data poped out of the other side of the fifo as needed by the uart.