In the Intel software developers manual it says that interrupt vectors 32-255 are usually user defined for external IO devices. In my systems programming class I must develop a simple device driver. My question is how can I define a specific interrupt vector to be used for a specific device? Is this done with the BIOS?
Note: we are developing a simple operating system so my situation is quite specific, however, in the end I need to understand how this all happens on an x86 system. Currently our system is set up so that a few interrupt vectors above 32 are assigned to devices like a serial port and keyboard. In reading the datasheet for the Intel 82801EB ICH5 IO controller, specifically the section concerning the 8259 PICs, it says that IRQ15 is the secondary IDE channel. How would that eventually be put on the stack as a interrupt vector?
I may just be so confused that this question didn't make sense, so I apologize in advance.
EDIT: So our systems programming class has a very simple OS, which has kernel routines for installing ISRs to handle specific interrupts given the vector number. In our class last quarter the professor gave us a header file that defined the keyboard as vector number 0x2c or something similar. I am trying to find out how to map the primary and/or secondary IDE channel interrupts to various ISRs using our kernel routines. For now, all of the unused interrupt vectors have a default handler that would print messages if an interrupt occurred, so IDE interrupts aren't even on at the moment, however that is another question.
Well, I seem to have found the answer in our support code, specifically the PIC initialization routine. With the following code IRQ lines are mapped at offset 20h and 28h in the IDT for the master and slave PICs, respectively.
/*
ICW2: master offset of 20 in the IDT, slave offset of 28
*/
__outb( PIC_MASTER_IMR_PORT, 0x20 );
__outb( PIC_SLAVE_IMR_PORT, 0x28 );
This means that the keyboard was mapped to vector number 2c and the primary and secondary channels will be mapped to 2e and 2f respectively. Some of you probably could have given me better answers had I asked the question better, but I appreciate the help anyway!
Table 45 of the 82801EB ICH5 datasheet details the 8259's IRQ lines, and in my OS the master is simply loaded at offset 20h and the slave is 28h.
Thanks!