Is it possible to disable Upwards name referencing in system-verilog? For example such that a lint error or compilation warning/error is raised if it's used in the source code?
Background: Using Upwards name referencing (as defined by 23.8 Upwards name referencing in the IEEE 1800-2017 SystemVerilog LRM) causes the module to be very dependent on the hierarchical position it's instantiated in. Therefore I want to avoid it in our codebase.
Anything is possible in software with the right amount of resources. But the current SystemVerilog LRM does not have such a feature. A decent lint tool could implement such a check. But...
Any hierarchical reference could be an upward reference and you wouldn't be able to detect without full elaboration of the design. Also, the top-level module is actually an upward reference, so you would need an exception for that