Implement a circuit that illuminates an LED when an odd number of the eight slide switches are set to “1”.
This is the project that I am trying. Only one solution came to my mind without using libraries (I don't know libraries yet). And it is assigning the led to all switch combinations.
Any idea how to optimize the code with/without using IEEE library?
`timescale 1ns / 1ps
module challenge1(
input [7:0] sw,
output [1:0] led
);
assign led[0] = ( ~sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & sw[4] & ~sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & sw[4] & ~sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & sw[4] & ~sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & sw[4] & sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & sw[4] & sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & sw[4] & sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & ~sw[5] & sw[4] & sw[3] & sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & ~sw[4] & ~sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & ~sw[4] & ~sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & ~sw[4] & sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & ~sw[4] & sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & ~sw[4] & sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & ~sw[4] & sw[3] & sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & sw[4] & ~sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & sw[4] & ~sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & sw[4] & ~sw[3] & sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & sw[4] & sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & sw[4] & sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & sw[4] & sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & ~sw[6] & sw[5] & sw[4] & sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & ~sw[4] & sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & ~sw[4] & sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & ~sw[4] & sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & ~sw[4] & sw[3] & sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & sw[4] & ~sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & sw[4] & ~sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & sw[4] & ~sw[3] & sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & sw[4] & sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & sw[4] & sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & sw[4] & sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & ~sw[5] & sw[4] & sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & ~sw[4] & ~sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & ~sw[4] & ~sw[3] & sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & ~sw[4] & sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & ~sw[4] & sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & ~sw[4] & sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & ~sw[4] & sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & sw[4] & ~sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & sw[4] & ~sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & sw[4] & ~sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & sw[4] & sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & sw[4] & sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & sw[4] & sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( ~sw[7] & sw[6] & sw[5] & sw[4] & sw[3] & sw[2] & sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & ~sw[4] & sw[3] & sw[2] & sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & sw[4] & ~sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & sw[4] & ~sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & sw[4] & ~sw[3] & sw[2] & sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & sw[4] & sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & sw[4] & sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & sw[4] & sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & ~sw[5] & sw[4] & sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & ~sw[4] & ~sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & ~sw[4] & ~sw[3] & sw[2] & sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & ~sw[4] & sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & ~sw[4] & sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & ~sw[4] & sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & ~sw[4] & sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & sw[4] & ~sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & sw[4] & ~sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & sw[4] & ~sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & sw[4] & sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & sw[4] & sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & sw[4] & sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & ~sw[6] & sw[5] & sw[4] & sw[3] & sw[2] & sw[1] & sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & ~sw[4] & ~sw[3] & sw[2] & sw[1] & sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & ~sw[4] & sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & ~sw[4] & sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & ~sw[4] & sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & ~sw[4] & sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & sw[4] & ~sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & sw[4] & ~sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & sw[4] & ~sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & sw[4] & sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & sw[4] & sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & sw[4] & sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & ~sw[5] & sw[4] & sw[3] & sw[2] & sw[1] & sw[0] ) |
( sw[7] & sw[6] & sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & sw[5] & ~sw[4] & ~sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( sw[7] & sw[6] & sw[5] & ~sw[4] & ~sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & sw[6] & sw[5] & ~sw[4] & ~sw[3] & sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & sw[5] & ~sw[4] & sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & sw[6] & sw[5] & ~sw[4] & sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & sw[5] & ~sw[4] & sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & sw[5] & ~sw[4] & sw[3] & sw[2] & sw[1] & sw[0] ) |
( sw[7] & sw[6] & sw[5] & sw[4] & ~sw[3] & ~sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & sw[6] & sw[5] & sw[4] & ~sw[3] & ~sw[2] & sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & sw[5] & sw[4] & ~sw[3] & sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & sw[5] & sw[4] & ~sw[3] & sw[2] & sw[1] & sw[0] ) |
( sw[7] & sw[6] & sw[5] & sw[4] & sw[3] & ~sw[2] & ~sw[1] & ~sw[0] ) |
( sw[7] & sw[6] & sw[5] & sw[4] & sw[3] & ~sw[2] & sw[1] & sw[0] ) |
( sw[7] & sw[6] & sw[5] & sw[4] & sw[3] & sw[2] & ~sw[1] & sw[0] ) |
( sw[7] & sw[6] & sw[5] & sw[4] & sw[3] & sw[2] & sw[1] & ~sw[0] ) ;
endmodule
As far as I know there are no IEEE libraries to assist in coding this if you want to use Verilog or SystemVerilog. Verilog and SystemVerilog are IEEE standards, Verilog is IEEE 1364-2005, SystemVerilog is IEEE 1800-2017.
Here are two methods using Verilog, which are concise relative to the posted code.
Method 1 was provided by @mkrieger1 in the post comments, and is obviously the most concise. The related concept of parity is worth researching and understanding if you don't know what it is and how it is used.
Read down the code to see Method 2 using a for loop.
module challenge1(
input [7:0] sw,
output [1:0] led
);
reg [3:0] ones_count = 0;
wire led_0;
// Method 1, xor reduction, AKA even parity
assign led_0 = ^sw;
// Method 2, loop over the vector, count the ones
always @(*) begin
ones_count = 0;
for(integer i = 0; i < 7 ; i++)
if(sw[i] == 1'b1)
ones_count = ones_count + 1;
else
ones_count = ones_count;
end
//
assign led[0] = ones_count[0];
assign led[1] = 1'b0;
endmodule
A testbench
module challenge1_tb();
reg [7:0] sw;
reg [1:0] led;
integer i;
initial begin
$monitor("sw = %b, dut.ones_count = %0d, led[0] = %b, dut.led_0 =%b",sw,dut.ones_count,led[0],dut.led_0);
for(i = 0; i < 8 ; i++) begin
sw = i;
#1;
end
end
challenge1 dut(
.sw(sw),
.led(led)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule
Produces
sw = 00000000, dut.ones_count = 0, led[0] = 0, dut.led_0 =0
sw = 00000001, dut.ones_count = 1, led[0] = 1, dut.led_0 =1
sw = 00000010, dut.ones_count = 1, led[0] = 1, dut.led_0 =1
sw = 00000011, dut.ones_count = 2, led[0] = 0, dut.led_0 =0
sw = 00000100, dut.ones_count = 1, led[0] = 1, dut.led_0 =1
sw = 00000101, dut.ones_count = 2, led[0] = 0, dut.led_0 =0
sw = 00000110, dut.ones_count = 2, led[0] = 0, dut.led_0 =0
sw = 00000111, dut.ones_count = 3, led[0] = 1, dut.led_0 =1
If you are able to use SystemVerilog, then the method $countones() can
be used. The use is similar to above, except that the for loop is replaced with ones_count = $countones(sw);
Yet another method is to use SystemVerilog's foreach([<vector>]) statement which is a little nicer replacement for the Verilog for() loop.