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macrossystem-verilog

How to create a macro for a string variable

How can I use a variable for a macro definition in system verilog: Example:

string string_var = "Hello"
define STRING_VAR_MACRO string_var

I want to make STRING_VAR_MACRO be Hello instead of string_var. Is there another way to achieve this? I don't want to do define STRING_VAR_MACRO Hello either for the purpose of my project

or the other option is I want string_var variable to be accessible globally through all files/modules

Solution

  • The way to make any variable globally accessible is putting in a package and referencing it explicitly or importing the package

    package gbls;
  string string_var = "Hello"
endpackage
module my_module;
  initial $display(gbls::string_var);
endmodule