SystemVerilog: Class function without parenthesis - call or scope

Question

I have been trying to see what class function calls in SystemVerilog without parenthesis resolve into.

say, what should this resolve into: class_inst.func_name.abc

Case 1: func_name returns a struct in which abc is a member.

Case 2: func_name has a static variable named abc.

Case 3: Both of above are true.

Case 4: func_name has a non-static variable named abc.

PS: we can assume abc is always type compatible.

VCS gives no error in Cases 1-3 but gives error in Case 4.

Question:

1. In case 3, what would class_inst.func_name.abc resolve into? static variable or return type?
2. Is VCS behavior correct?
3. Is there any other case I am missing?

Answer 1

The proposed 1800-2023 SystemVerilog LRM has recently clarified this as part of an enhancement that allows function call chaining.

Without parenthesis, this is a hierarchical scope reference. This is backward compatible with legacy Verilog. Hierarchical references are allowed to static variables and nets from almost anywhere. You cannot reference automatic variables from outside their declarative scope. The reference is from within the scope of the function, not within the type of the return value. I get an error for case 1 on all simulators on EDAPlayground.

If parenthesis follow func_name, that is always a function call and required for function chaining.

module top;
  typedef struct {int A,B;} AB_t;
  
  function AB_t foo;
    static int B = 3;
    foo = '{1,2};
  endfunction
  
  initial begin
    void'(foo());
 // $display(foo.A); // case 1 is an error
    $display(foo.B); // case 2 & 3
  end
endmodule