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system-veriloghardwaretest-bench

SV method which can monitor any digital signal from 1bit...128bit


I have a testbench SV task that can check the frequency of a 1 bit logic signal, useful to measure frequencies of clocks, valids etc... however how can I measure the frequency of a multi-bit data signal to get a rough idea of how fast samples are changing.

The problem is I don't want to care about the signal size but the compiler does. Is there anyway to pass an unspecified size logic signal into a SV task? e.g.

  task automatic chk_data_rate(
    ref int signal, 
    input time timeout,
    output real meas_freq
  );
    : : :
  endtask

  real f;
  logic [23:0] a;
  logic [7:0] b;
  logic [31:0] c;
  chk_data_rate(a, 1ms, f);  
  chk_data_rate(b, 1ms, f);
  chk_data_rate(c, 1ms, f);

Here the error is:

xmelab: *E,TYCMPAT (test.sv,1769|38): ref formal and actual do not have equivalent data types on instance '$unit_0x78c03c36' (expecting datatype compatible with 'int' but found 'packed array [23:0] of logic' instead).

I can change int the same type as 'a' but I can't make it generic...

I could convert each signal to analyse into a single bit first and then use existing task, but it seems cumbersome...


Solution

  • I'd suggest using parameterized classes to do it. Something like in the following example:

    module mod;
      class abc #(size = 1);
        logic [size-1:0] data;
        function new();
        endfunction
        
        task monitor();
          $display("my size is %0d", size);
        endtask
      endclass
    
      abc #(24) a = new;
      abc #(8) b = new;
      abc #(63) c = new;
      
      initial begin
        a.monitor;
        b.monitor;
        c.monitor;
      end
    endmodule