I have the following array in SystemVerilog:
reg [49:0] wvu[0:63] = {
50'b00001111111101100111101111101010000010000000110011,
50'b00000000000000000000000000000000000000000000000000,
50'b00000000000001000000100100011111110001101001111010,
//...
50'b01111111111111111111111111111111011101111111111111
};
The bit width of 50 and the 64 elements are not fixed numbers and they can be different for a different application. It is not desirable to change the bit width for different applications, therefore I have fixed it to 32 bits:
reg [31:0] wvu_prime [0:100] = {
32'b00001111111101100111101111101010,
32'b00001000000011001100000000000000,
32'b00000000000000000000000000000000,
32'b00000000000000000100000010010001,
32'b11111100011010011110100000000000,
//...
32'b00000000000000011111111111111111,
32'b11111111111111011101111111111111
};
The data of wvu and wvu_prime is the same and if I would concatinate all elements of wvu and concatinate all elements of wvu_prime, they would both become two 3200 bit regs which are exactly the same.
Now my question is, how can I get data from wvu_prime with the indexes of wvu? For example, I can access the range of bits y:z of element x of wvu using wvu[x][y:z]. How can I get the same data from wvu_prime? Result should be synthesizable.
You can use a packed union for this.
union packed {
logic [0:63][49:0] wvu;
logic [0:99][31:0] wvu_prime;
} data;
Then for example, you can access data.wvu[3][10:5] which maps to {data.wvu_prime[5][2:0],data.wvu_prime[6][31:29]}.
This should be synthesizable, but I would check with your tool before getting too far into your design. Also check for timing and area. You may need to break this up into multiple clock cycles.