Why can I use module low(.A(a),.B(b)); in module declaration？

Question

I feel confused when I see this in the IEEE Verilog 2001 Standard. Why can I use module low(.A(a),.B(b)); in a module declaration？

module_declaration ::= (From Annex A - A.1.3)
{ attribute_instance } module_keyword module_identifier [ module_parameter_port_list ]
[ list_of_ports ] ; { module_item }
endmodule

list_of_ports ::= ( port { , port } )

port ::= [ port_expression ] | . port_identifier ( [ port_expression ] )

Isn't this named port connection supposed to be used for module instantiation, and why is it used for module declarations？ There is some code like this module complex_ports ({c,d}, .e(f));

Answer 1

The reason for that is to be able to separate internal names of the module ports from external names. It is explained in the following example:

module mod(.a(ina), .b(outb));
  input wire ina;  // << internal name
  output reg outb;
  
  always @*
    outb = ina;
endmodule

module top();
  reg topa;
  wire topb;
  mod mod(.a(topa), .b(topb)); // << use externa names
endmodule   

In the above example the feature is not very interesting. It probably can be used to standardize external port names. However, there is one interesting implication, an ability to connect internal 'net' variable to multiple ports:

module mod(.a1(ina[0]), .a2(ina[1]), .b(outb));
  input  wire [1:0] ina;  // << internal vector net connected to a1 and a2
  output reg [1:0] outb;
  
  always @*
    outb = ina;
endmodule

module top();
  reg topa1, topa2;
  wire [1:0] topb;
  mod mod(.a1(topa1), .a2(topa2), .b(topb)); // << use externa names
endmodule