Using this systemverilog snip to change bytes to 16 bit words.
module tb();
logic [31:0] myWordQueue[$];
byte myByteQueue [$];
initial begin
$display("starting");
myByteQueue[0] = 8'h44;
myByteQueue[1] = 8'h94;
myByteQueue[2] = 8'h03;
myByteQueue[3] = 8'h00;
myByteQueue[4] = 8'hb8;
myByteQueue[5] = 8'h99;
myByteQueue[6] = 8'h03;
myByteQueue[7] = 8'h00;
myWordQueue = {>>32{myByteQueue}};
$display("myWordQueue[0] = %h", myWordQueue[0] );
$display("myWordQueue[1] = %h", myWordQueue[1] );
end
endmodule
Which produces
# myWordQueue[0] = 44940300
# myWordQueue[1] = b8990300
How do I change the streaming operator such that the pattern produced is:
myWordQueue[0] = 00039444
myWordQueue[1] = 000399b8
Also tried
myWordQueue = {<<32{myByteQueue}};
Also does not produce the result I need.
You need to nest the streaming operator. First to reverse the byte order, then to reverse the word order.
myWordQueue = {<<32{ {<<8{myByteQueue}} }} ;
Note that when using right-to-left streaming >>N
the N
has no effect.