Let's say I have the following:
type slv1_array is array (natural range <>) of std_logic_vector(0 downto 0);
type slv2_array is array (natural range <>) of std_logic_vector(1 downto 0);
type slv3_array is array (natural range <>) of std_logic_vector(2 downto 0);
type slv4_array is array (natural range <>) of std_logic_vector(3 downto 0);
type slv5_array is array (natural range <>) of std_logic_vector(4 downto 0);
type slv6_array is array (natural range <>) of std_logic_vector(5 downto 0);
type slv7_array is array (natural range <>) of std_logic_vector(6 downto 0);
type slv8_array is array (natural range <>) of std_logic_vector(7 downto 0);
type slv9_array is array (natural range <>) of std_logic_vector(8 downto 0);
...
Is there a general way in VHDL-2008 to specify the conversion between any of these types without defining conversion functions for every possible permutation?
No, there is not. Each array you have created is a specific type, and hence the lengths all mismatch, so a "general way" would not be appropriate - how would you assign a 4 bit vector to a 5 bit vector, for example?
But VHDL-2008 does support unconstrained arrays. Having to have so many types of arrays with different length elements is frustrating. So instead, why no just declare:
type slv_array_t is array(natural range <>) of std_logic_vector; -- element unconstrained, allowed in 2008
then when you declare an object, you can constrain both dimensions:
signal slv8_8 : slv_array_t(0 to 7)(7 downto 0);
signal slv16_16 : slv_array_t(15 downto 0)(15 downto 0);
now slv8_8 and slv16_16 have the same base type, which can be useful in testbenches, with things like access types.
type slv_array_ptr_t is access slv_array_t;
variable v1 : slv_array_ptr_t;
...
v1 := new slv_array_t'(slv8_8);
v1 := new slv_array_t'(slv16_16);
doing this in 1993 would not be possible, access types for each of your types would be required, and hence separate variable objects to store them. VHDL 2008 allows much easier transfer.