Error: "Syntax in assignment statement l-value." while trying to assign a reg inside an always block

Question

I'm trying to model a circuit. Here is the code of the circuit I'm trying to build. I get the error inside the always block and specifically inside the cases. I'm trying to assign reg NextState to a specific state; however I get an error.

module seq(x_in,y_out,Clk,reset);
    input x_in ,Clk, reset;
    output reg y_out;
    reg  [1:0]NextState;
    reg [1:0]CurrentState;

    parameter stateA = 2'b00,
              stateB = 2'b01,
              stateC = 2'b10,
              stateD = 2'b11;

    always @(x_in or CurrentState) begin
        NextState = stateA;
        y_out = 1'b0;

        case(CurrentState)
           a : begin
            if(x_in) 
             NextState = stateC;
             y_out = 1'b0;
            else
             NextState = stateB;
             y_out = 1'b1; 
           end
           b : begin
            if(x_in)
             NextState = stateD;
             y_out = 1'b1;
            else
             NextState = stateC;
             y_out = 1'b0;
           end
           c : begin
            if(x_in)
             NextState = stateD;
             y_out = 1'b1;
            else
             NextState = stateB ;
             y_out = 1'b0;
           end
           d : begin
            if(x_in)
             NextState = stateA;
             y_out = 1'b0;
            else
             NextState = stateC;
             y_out = 1'b1;
           end
           default : begin
             y_out = 1'bx;
             NextState = 2'bxx;
           end
        endcase
    end

    always @(negedge reset ,posedge Clk) begin
     if(!reset)
     CurrentState <= stateA;
     else
     CurrentState <= NextState;
    end
    
endmodule

During compilation I get the error described in the title in multiple lines inside the always block.

seq.v:22: syntax error
seq.v:23: Syntax in assignment statement l-value.
seq.v:30: syntax error
seq.v:31: Syntax in assignment statement l-value.
seq.v:38: syntax error
seq.v:39: Syntax in assignment statement l-value.
seq.v:46: syntax error
seq.v:47: Syntax in assignment statement l-value.
Compilation finished with exit code 8

Answer 1

You have two types of syntax errors.

You are missing the begin/end keywords inside the if/else statements in each case item.

Your case items use undeclared identifiers: a instead of stateA.

For example, change:

    case(CurrentState)
       a : begin
        if(x_in) 
         NextState = stateC;
         y_out = 1'b0;
        else
         NextState = stateB;
         y_out = 1'b1; 
       end

to:

    case(CurrentState)
       stateA : begin
        if(x_in) begin       // add begin
         NextState = stateC;
         y_out = 1'b0;
        end else begin      // add begin and end
         NextState = stateB;
         y_out = 1'b1; 
        end                 // add end
       end

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The iverilog errors are not very specific. You can usually get more meaningful errors on different simulators, like those on EDA Playground