Trying to design a simple MAC Unit in VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MAC is
port (
DIN: IN signed(15 downto 0);
WEIGHT: IN signed(15 downto 0);
CLK: IN std_logic;
RST: IN std_logic;
RESULT: OUT signed(15 downto 0);
);
end entity MAC;
architecture base of MAC is
begin
process(CLK)
variable acc_value : signed(15 downto 0);
begin
IF rising_edge(CLK) then
IF RST='1' THEN
acc_value := (OTHERS => '0'); -- reset accumulated value to 0
ELSE
acc_value := (acc_value + WEIGHT* DIN);
RESULT <= acc_value;
END IF;
END IF;
END process;
end base;
Seems like there is a problem with acc_value := (acc_value + WEIGHT* DIN);
.
There is an error in the simulation "ERROR: Array sizes do not match, left array has 16 elements, right array has 32 elements" with confuses me, because for me both arrays have 16 bits (or?)
It's because of overflowing, you need to take care of that.
acc_value := (acc_value + WEIGHT* DIN);
In the right hand side, WEIGHT * DIN
is 16 bit * 16 bit = 32 bits. Adding the 16-bit acc_value
to that (acc_value + WEIGHT*DIN
) gives you a 32-bit value, which cannot be assigned into the 16-bit variable signed acc_value
.