How do I implement the code for an unsigned 4-bit multiplier

Question

I am trying to create a 4-bit multiplier using behavioral Verilog with assignment statements and procedural blocks if possible. The circuit I am trying to replicate is this one :

So far, I defined the submodule fouralu_adder which is a simple unsigned 4-bit adder. Then I wrote the following psuedo-code:

module fouralu_multi(
    input [3:0] A_i,//Input signals
    input [3:0] B_i,
    output [7:0] S_o//Output signal 
    );
    wire [4:0] S1,S2;//These were supposed to be the SUM wires coming out of AD1 and AD2
    wire [3:0] AND; 
    fouralu_adder AD1(
    //Port connections here
    );
     
    fouralu_adder AD2(
    //Port connections here
    );
    fouralu_adder AD3(
       //Port connections here
    );
endmodule

The initial idea I had was to somehow assign the behavior of the and gates with something like : assign AND = A_i&B_i[0]; then repeat for each value of B_i but quickly realized it would be quite an inefficient approach. This leads me to ask the question : How do I implement the circuit using behavioral verilog? How am I to connect the input ports to the submodule without using structural verilog, and with as little wire variables as possible? Thank you in advance for your help

Answer 1

You can use for loop, google it and you'll learn how to use it.

For example

integer idx;

reg [3:0] A_AND_B [0:3];

always @(*)begin
    for( idx=0; idx<4; idx=idx+1) A_AND_B[idx] = {4{B[idx]}} & A;
end

this code equals to

reg [3:0] A_AND_B [0:3];

always @(*)begin
    A_AND_B[0] = {4{B[0]}} & A;
    A_AND_B[1] = {4{B[1]}} & A;
    A_AND_B[2] = {4{B[2]}} & A;
    A_AND_B[3] = {4{B[3]}} & A;
end